Control system modelling in VHDL 2008

• From 64-bit floating-point to custom fixed-point.

  • OSVB: fpconv: data type exploration and visualization in arithmetic algorithms/circuits.

• From a single process to a spatial synthesizable design.

  • Clocking schemes.

• Passing complex generics/parameters through JSON-for-VHDL.

• From an isolated core to a software-hardware partitioned design.

  • Introduction to VUnit’s AXI verification components.

  • Direct cosimulation: VHDL and C/Python.

TBC