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Co-simulation and behavioural verification with VHDL, C/C++ and Python/m
Logo
  • Home
  • VHDL, a programming language
  • Hardware-software co-design
  • Installation of FLOSS EDA tools

Exercises

  • GHDL Quick Start Guide and VUnit User Guide
  • Matrices, AXI4 Stream Verification Components and cosimulation
  • Control system modelling in VHDL 2008
  • Logging
  • HSCES
  • Octave
  • Xyce

Appendix

  • Slides
  • Development Environment 101
  • Apache License 2.0
  • Creative Commons Attribution 4.0 International
  • References
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Development Environment 101¶

  • missing.csail.mit.edu: The Missing Semester of Your CS Education

  • lab.github.com

  • The UNIX Game

  • Open Source Society University: Computer Science

  • debuggingbook.org

Git¶

  • guides.github.com

    • Git Handbook

    • Understanding the GitHub flow

  • training.github.com: Git Cheat Sheets

  • git-school.github.io: Visualizing Git

  • learngitbranching.js.org

  • Git-it

  • ohshitgit.com

  • Flight rules for Git

Python¶

  • gh:satwikkansal/wtfpython

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Apache License 2.0
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  • Development Environment 101
    • Git
    • Python