References

[R1]

missing author in 1076-2008

[R2]

ghdl-yosys-plugin: VHDL synthesis (based on ghdl and yosys). 2017. URL: https://github.com/ghdl/ghdl-yosys-plugin.

[R3]

Lars Asplund, Olof Kraigher, and contributors. VUnit: a unit testing framework for VHDL/SystemVerilog. Sep 2014. URL: http://vunit.github.io.

[R4]

Tony Bybell and contributors. GTKWave: a is a fully featured GTK+ based wave viewer for Unix, Win32, and Mac OSX. 1998. URL: https://github.com/gtkwave/gtkwave.

[R5]

Wolf Clifford and Johann Glaser. A Free Verilog Synthesis Suite. In Proceedings of Austrochip 2013. 2013.

[R6]

Tristan Gingold and contributors. GHDL: open-source analyzer, compiler, simulator and (experimental) synthesizer for VHDL. Sep 2003. URL: https://github.com/ghdl/ghdl.