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Co-simulation and behavioural verification with VHDL, C/C++ and Python/m
Logo
  • Home
  • VHDL, a programming language
  • Hardware-software co-design
  • Installation of FLOSS EDA tools

Exercises

  • GHDL Quick Start Guide and VUnit User Guide
  • Matrices, AXI4 Stream Verification Components and cosimulation
  • Control system modelling in VHDL 2008
  • Logging
  • HSCES
  • Octave
  • Xyce

Appendix

  • Slides
  • Development Environment 101
  • Apache License 2.0
  • Creative Commons Attribution 4.0 International
  • References
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