Glossary and acronyms

  • API: Application Programming Interface (see Wikipedia: Application programming interface).

  • ABI: Application Binary Interface (see Wikipedia: Application binary interface).

  • BFM: Bus Functional Model.

  • cocotb: a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python [6].

  • DPI: Direct Programming Interface. SystemVerilog DPI is an interface which can be used to interface SystemVerilog with foreign languages (see Wikipedia: SystemVerilog DPI).

  • DUT: Design Under Test.

  • FFI: Foreign Function Interface, a mechanism by which a program written in one programming language can call routines or make use of services written in another (see Wikipedia: Foreign function interface).

  • FIFO: First In First Out, a method for organising the manipulation of a data structure where the oldest (first) entry, or head of the queue, is processed first (see Wikipedia: FIFO (computing and electronics)).

  • FLI: Foreign Language Interface. Mentor Graphics’ ModelSim/Questa tools implement an interface named VHDL FLI: “FLI routines are C programming language functions that provide procedural access to information within Model Technology’s HDL simulator, vsim”.

  • FOSS/FLOSS: Free/Libre and Open Source Software.

  • GCC: the GNU Compiler Collection [7].

  • GDB: the GNU Project Debugger [8].

  • GHDL: open-source analyzer, compiler, simulator and (experimental) synthesizer for VHDL [9].

  • GRT: GHDL’s RunTime library.

  • HDL: Hardware Description Language.

  • HLS: High Level Synthesis.

  • IEEE: Institute of Electrical and Electronics Engineers (see

  • IR: Intermediate Representation.

  • LCS: Language Change Specification.

  • LLVM: a compiler infrastructure designed around a language-independent IR [10].

  • OSVVM: Open Source VHDL Verification Methodology [1].

  • PLI: Program Language Interface. PLI was superseeded by VPI in IEEE Std 1364-2005, sometimes referred to as PLI 2.

  • PPC: commonly used to refer to PowerPC and/or Power ISA processors.

  • PSL: Property Specification Language, IEEE Std 1850, incorporated in IEEE Std 1076-2008 (see Wikipedia: Property Specification Language).

  • QEMU: a generic and open source machine emulator and virtualizer.

  • RPC: Remote Procedure Call.

  • RTL: Register-Transfer Level.

  • UUT: Unit Under Test.

  • VASG: VHDL Analysis and Standardization Group (see

  • VC: Verification Component.

  • Verilator: FLOSS tool for converting Verilog to a cycle-accurate behaviour model in C++ or SystemC [2].

  • Verilog: a HDL, IEEE Std 1364. In 2009, it was merged into the SystemVerilog standard creating IEEE Std 1800 (see Wikipedia: Verilog).

  • VHDL: VHSIC-HDL, Very High Speed Integrated Circuit Hardware Description Language, IEEE Std 1076 (see Wikipedia: VHDL).
    • Revisions: 1987, 1993, 2000, 2002 (IEC 61691-1-1:2004), 2008 (IEC 61691-1-1:2011), 2019.
    • Related standards:
      • 1076.1 VHDL Analog and Mixed-Signal (VHDL-AMS)
      • 1076.1.1 VHDL-AMS Standard Packages (stdpkgs)
      • 1076.2 VHDL Math Package
      • 1076.3 VHDL Synthesis Package (vhdlsynth) (numeric_std)
      • 1076.3 VHDL Synthesis Package – Floating Point (fphdl)
      • 1076.4 Timing (VHDL Initiative Towards ASIC Libraries: vital)
      • 1076.6 VHDL Synthesis Interoperability (withdrawn in 2010)[11]
      • 1164 VHDL Multivalue Logic (std_logic_1164) Packages
  • VHPI: VHDL Procedural Interface, incorporated in IEEE Std 1076-2008.

  • VPI: Verilog Procedural Interface, incorporated in IEEE Std 1364-2005 (see Wikipedia: Verilog Procedural Interface).

  • VUnit: an open source unit testing framework for VHDL/SystemVerilog [11].

  • XSI: Xilinx Simulator Interface, “a C/C++ application programming interface (API) to the Xilinx Vivado Simulator (xsim) that enables a C/C++ program to serve as the test bench for a HDL design[12].


[1] J. Lewis and contributors, “Open Source VHDL Verification Methodology (OSVVM),” May 2013.

[2] W. Snyder and contributors, “Verilator, FOSS tool which converts Verilog to a cycle-accurate behavioral model in C++ or SystemC,” 2003.

[6] C. Higgs, S. Hodgson, and contributors, “Coroutine Cosimulation TestBench (cocotb),” Jun. 2013.

[7] R. Stallman and contributors, “GCC, the GNU Compiler Collection,” May 1987.

[8] R. Stallman and GNU Project, “GDB: The GNU Project Debugger,” 1986.

[9] T. O. Gingold and contributors, “GHDL: open-source analyzer, compiler, simulator and (experimental) synthesizer for VHDL,” 2003.

[10] V. Adve, C. Lattner, and LLVM Developer Group, “LLVM Project, a collection of modular and reusable compiler and toolchain technologies,” 2003.

[11] L. Asplund, O. Kraigher, and contributors, “VUnit: a unit testing framework for VHDL/SystemVerilog,” Sep. 2014.

[12] Xilinx, “UG900 (v2018.3) Vivado Design Suite User Guide, Logic Simulation,” 2018.